Injection method with schottky source/drain

ABSTRACT

An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 12/430,817(Att. Docket P970074), filed on Apr. 27, 2009 and entitled INJECTIONMETHOD WITH SCHOTTKY SOURCE/DRAIN, now U.S. Pat. No. 8,183,617, theentire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates generally to semiconductor fabricationmethods and, more particularly, to the fabrication of non-volatilememory devices.

2. Description of Related Art

Non-volatile MOS memory cells having a source and a drain disposed in asubstrate and controlled by a gate may store data by trapping charges ina dielectric region of the gate. An unprogrammed cell may havesubstantially no charges trapped in the dielectric. A cell may beprogrammed by applying suitable programming voltages to the source,drain, and gate. The programming voltages may create an electric fieldin a channel between the source and drain that imparts energy to chargesin the channel, enabling them to reach the dielectric region. Thecharges may become trapped in the dielectric region, thereby changing athreshold voltage of the cell. Forward and reverse reading methods areknown by which the threshold voltage may be measured in order todetermine whether a cell is programmed or unprogrammed. Some memorycells may store charge in separate portions of the dielectric region,thereby effectively storing more than one bit per cell.

With scaled-down geometries, parasitic effects that may negativelyaffect performance of devices employing non-volatile MOS memory cellsmust be considered. For example, a short channel effect andpunch-through issues are known to be detrimental to memory celloperation. Lower programming efficiency when channel hot electronprogramming is employed may also result due to a degraded lateralelectric field.

A need exists in the prior art for structures and methods that provideimmunity from scaling issues in non-volatile MOS memory cells.

SUMMARY OF THE INVENTION

The present invention addresses this need by providing, according to oneaspect, a semiconductor non-volatile memory cell comprising a substrate,a source fabricated of silicide material in an upper surface of thesubstrate, a drain likewise fabricated of silicide material in an uppersurface of the substrate, and a gate comprising an oxide-nitride-oxide(ONO) layer and disposed nominally between the source and the drain, thegate being fabricated at a level higher than the source and the drain,wherein a Schottky barrier is formed at an interface between thesubstrate and the silicide material of the source and at an interfacebetween the substrate and the silicide material of the drain. In oneembodiment of the semiconductor non-volatile memory cell the gatefurther comprises silicon. In another embodiment of the semiconductornon-volatile memory cell the gate comprises a silicide and the ONOlayer. In yet another embodiment of the semiconductor non-volatilememory cell the gate comprises metal and the ONO layer. An embodiment ofthe semiconductor non-volatile memory cell has the Schottky barriercontrolled by a position of the gate relative to a position of thesource and to a position of the drain. In a particular embodiment of thesemiconductor non-volatile memory cell, the gate is disposed above andbetween the source and the drain, a vertical extension of an edge of thesource nearest the gate does not intersect the gate and a verticalextension of an edge of the drain nearest the gate does not intersectthe gate.

While the apparatus and method has or will be described for the sake ofgrammatical fluidity with functional explanations, it is to be expresslyunderstood that the claims, unless expressly formulated under 35 U.S.C.§112, are not to be construed as necessarily limited in any way by theconstruction of “means” or “steps” limitations, but are to be accordedthe full scope of the meaning and equivalents of the definition providedby the claims under the judicial doctrine of equivalents, and in thecase where the claims are expressly formulated under 35 U.S.C. §112 areto be accorded full statutory equivalents under 35 U.S.C. §112.

Any feature or combination of features described herein are includedwithin the scope of the present invention provided that the featuresincluded in any such combination are not mutually inconsistent as willbe apparent from the context, this specification, and the knowledge ofone skilled in the art. In addition, any feature or combination offeatures may be specifically excluded from any embodiment of the presentinvention. For purposes of summarizing the present invention, certainaspects, advantages and novel features of the present invention aredescribed. Of course, it is to be understood that not necessarily allsuch aspects, advantages or features will be embodied in any particularimplementation of the present invention. Additional advantages andaspects of the present invention are apparent in the following detaileddescription and claims that follow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A is a cross-sectional diagram of a non-volatile memory cell afterconventional storage layer and gate processes are performed;

FIG. 1B is a cross-sectional diagram of the non-volatile memory cell ofFIG. 1A following capping with a silicide material;

FIG. 1C is a cross-sectional diagram of the non-volatile memory cell ofFIG. 1B after formatting the silicide material to form a source, a drainand a gate in the memory cell;

FIG. 2A is a cross-sectional diagram of a non-volatile memory cellconfigured with terminals for programming;

FIG. 2B is an intrinsic energy band diagram for a non-volatile memorycell;

FIG. 2C is an energy band diagram for a non-volatile memory cell withsource/drain voltages applied;

FIG. 2D is a an energy band diagram for a non-volatile memory cell withgate and source/drain voltages applied;

FIG. 3A is a cross-sectional diagram of a Schottky device storing alocalized charge;

FIG. 3B is a plot of a simulated current-voltage (IV) characteristic ofthe Schottky device of FIG. 3A with electrons trapped near a source sideunder unprogrammed, forward read, and reverse read conditions;

FIG. 3C is a plot of a simulated IV characteristic of the Schottkydevice of FIG. 3A with holes trapped near a source side underunprogrammed, forward read, and reverse read conditions;

FIG. 4A is a plot of an experimental IV characteristic of the Schottkydevice of FIG. 3A under reverse read conditions;

FIG. 4B is a plot of an experimental IV characteristic of the Schottkydevice of FIG. 3A under forward read conditions;

FIG. 5A is a cross-sectional diagram of a non-volatile memory cellshowing a Schottky barrier modified with non-overlapping source/drainand gate structures;

FIG. 5B is a cross-sectional diagram of a non-volatile memory cellshowing a Schottky barrier modified with source/drain edgessubstantially aligned with gate edges;

FIG. 5C is a cross-sectional diagram of a non-volatile memory cellshowing a Schottky barrier modified with overlapping source/drain edgesand gate edges;

FIGS. 6A-6C are a collection of three flow diagrams depictingalternative methods of modifying a Schottky barrier;

FIGS. 7A a-7Cd are a collection of cross-sectional diagrams of anon-volatile memory cell portraying results of the methods of FIGS.6A-6C;

FIG. 8 is a flow diagram summarizing an implementation of anotheralternative method of modifying a Schottky barrier; and

FIGS. 9A-9F are a collection of cross-sectional diagrams of anon-volatile memory cell elucidating results of the implementation ofFIG. 8.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same or similar referencenumbers are used in the drawings and the description to refer to thesame or like parts. It should be noted that the drawings are insimplified form and are not presumed, automatically, to be to precisescale in all embodiments. That is, they are intended to be examples ofimplementations of various aspects of the present invention and,according to certain but not all embodiments, to be to-scale. While,according to certain implementations, the structures depicted in thesefigures are to be interpreted to be to scale, in other implementationsthe same structures should not, In certain aspects of the invention, useof the same reference designator numbers in the drawings and thefollowing description is intended to refer to similar or analogous, butnot necessarily the same, components and elements. According to otheraspects, use of the same reference designator numbers in these drawingsand the following description is intended to be interpreted as referringto the same or substantially the same, and/or functionally the same,components and elements. In reference to the disclosure herein, forpurposes of convenience and clarity only, directional terms, such as,top, bottom, left, right, up, down, over, above, below, beneath, rear,and front, are used with respect to the accompanying drawings. Suchdirectional terms should not be construed to limit the scope of theinvention in any manner.

Although the disclosure herein refers to certain illustratedembodiments, it is to be understood that these embodiments are presentedby way of example and not by way of limitation. The intent accompanyingthis disclosure is to discuss exemplary embodiments with the followingdetailed description being construed to cover all modifications,alternatives, and equivalents of the embodiments as may fall within thespirit and scope of the invention as defined by the appended claims. Itis to be understood and appreciated that the process steps andstructures described herein do not cover a complete process flow for themanufacture of the disclosed structures. The present invention may bepracticed in conjunction with various integrated circuit fabrication andother techniques that are conventionally used in the art, and only somuch of the commonly practiced process steps are included herein as arenecessary to provide an understanding of the present invention. Thepresent invention has applicability in the field of semiconductordevices and processes in general. For illustrative purposes, however,the following description pertains to a non-volatile memory device and arelated method.

Referring more particularly to the drawings, FIG. 1A is across-sectional diagram of a partially fabricated non-volatile memorycell after conventional storage layer and gate processes are performed.Known methods may be employed to fabricate an array of such cells in asubstrate 10 composed of for example, bulk silicon orsilicon-on-insulator (SOI). In some embodiments, the substrate 10 may belightly doped with p-type atoms; in other embodiments the substrate 10may be lightly doped with n-type atoms. A structure of a typicalnon-volatile memory cell fabricated using these methods may comprise astorage layer 15, which may comprise an oxide-nitride-oxide (ONO) layer.Other embodiments of the storage layer 15 may comprise, in addition tonitride, high-k dielectric material or any other kind of non-volatilecharge storage material. Examples of high-k dielectric material includehafnium silicate, zirconium silicate, hafnium dioxide and zirconiumdioxide. The structure, further, may comprise a gate structure 20 andinsulating spacers 25. Beginning with the structure of FIG. 1A, silicidematerial 30 may be applied over the structure FIG. 1A as illustrated inFIG. 1B, and a process (e.g., a thermal process) may be used to format asilicide resulting in a structure shown in FIG. 1C wherein the silicidedefines a source 35, a drain 40 and a gate contact 45. The ONO layer 15,the gate structure 20 and the gate contact 45 may be referred to as agate 21. The gate 21 is disposed nominally between the source 35 and thedrain 40 and typically lies at a higher level than either the source 35or the drain 40. In operation, bias conditions applied to the source,drain, and gate may result in conduction current coming from carriershaving energy sufficient to tunnel through a Schottky barrier, which ismore particularly described below. High-energy carriers from a sourceside of a channel that forms between the source and drain my also injectinto the storage layer 15 when the bias conditions produce a suitablevertical electric field.

FIG. 2A is a cross-sectional diagram of a non-volatile memory cellsimilar to that illustrated in FIG. 1C and including a schematicrepresentation of terminals that may be used to operate (e.g., programand/or read) the cell, Specifically, a source terminal 36, a drainterminal 41 and a gate terminal 46 are provided. Some embodiments alsomay include a substrate terminal 11, The non-volatile memory cell isillustrated with electrons 50 trapped in the storage layer 15 at asource side of the memory cell.

FIG. 2B is an intrinsic energy band diagram for a non-volatile memorycell. In an unbiased state, a Schottky barrier formed at a boundary of asemiconductor (e.g., substrate 10 in FIG. 2A) and a silicide (e.g.,suicide forming the source 35 and/or the drain 40 in FIG. 2A) iscontrolled by the silicide material. A source 35/substrate 10 boundary(i.e., a boundary between source 35 and substrate 10; FIG. 2A) isdesignated as 37; a drain 40/substrate 10 boundary is designated as 42.It should be noted that the Schottky barrier is ambipolar, which admitsboth p- and n-type substrates. When bias voltages are applied to thesource terminal 36 and the drain terminal 41, a channel may form in thesubstrate 10 between the source 35 and the drain 40. Under thiscondition, the Schottky barrier may bend as illustrated in FIG. 2C, andhot carriers in the channel with sufficient energy may tunnel throughthe Schottky barrier. With bias voltages applied to the gate terminal46, the source terminal 36 and the drain terminal 41, the Schottkybarrier may appear as illustrated in FIG. 2D. The gate, source, anddrain terminal voltages may be positive or negative, depending uponwhether positive or negative carriers are to be injected into thestorage layer 50. It should be emphasized that hot carriers are injectedinto the storage layer 15 at the source side, not the drain side, of thenon-volatile memory cell. Although various bias conditions can beintroduced to modify a Schottky barrier and, thereby, to controlefficiency of programming in a non-volatile memory cell, methodsdescribed herein may provide alternatives to conventional methods. Theherein-described methods avoid a high-temperature activation dosageprocess, so that short channel effect and punch-through aresubstantially eliminated as problem-causing issues. Rather, thesemethods employ a relatively low-temperature thermal silicidation processthat may provide much more elasticity of process issues than doconventional methods. Further, these methods may be relativelyinsensitive to device scaling.

FIG. 3A is a cross-sectional diagram of a Schottky device, i.e.,non-volatile memory cell, with localized charge stored near a sourceside of the cell. Embodiments of devices described below may supportphysical 2-bit operation. That is, electrons/holes may be independentlystored on a source side and a drain side of the cell. Three curvesrepresenting simulated current-voltage (IV) characteristics of the cellof FIG. 3A are shown in FIG. 3B for a case where the localized storedcharge comprises electrons. A first curve 60 corresponds to an IVcharacteristic of an unprogrammed cell. A second curve 65 corresponds toan IV characteristic of the cell having electrons stored near the sourceside under forward read conditions, and a third curve 70 corresponds anIV characteristic of the cell under reverse read conditions. Methods forreading non-volatile memory cells using forward read and reverse readtechniques are known to those skilled in the art.

A similar set of simulated IV characteristics of the cell of FIG. 3A isshown in FIG. 3C for a case where the localized stored charge comprisesholes. As before, a first curve 61 corresponds to an IV characteristicof an unprogrammed cell, and a second curve 66 corresponds to an IVcharacteristic of the cell having holes stored near the source sideunder forward read conditions. A third curve 71 corresponds to an IVcharacteristic of the cell under reverse read. conditions.

Experimental results corresponding to FIG. 3B are shown in FIGS. 4A and4B. FIG. 4A presents a first curve 80 corresponding to an IVcharacteristic of an unprogrammed cell under reverse read conditions. Asecond curve 85 in FIG. 4A corresponds to an IV characteristic of anon-volatile memory cell having electrons trapped near a source side.Forward read results are presented in FIG. 4B wherein a first curve 81corresponds to an IV characteristic of an unprogrammed cell, and asecond curve 86 corresponds to an IV characteristic of a cell havingelectrons trapped near the source side under forward read conditions.Approximate program bias voltages for the characteristics presented inFIGS. 4A and 4B include a gate voltage ranging from about zero to about10 volts, a source voltage ranging from about −5 to about 5 volts asubstrate voltage ranging from about −3 to about 3 volts, and drainvoltage ranging from about −3 to about 3 volts. Generally, the drainpotential may be higher than the source potential, and gate potentialmay be higher than the drain voltage. The experimental results of FIGS.4A and 4B may be noted to be consistent with the simulated results ofFIG. 3B, It should be emphasized that electrons are injected into thestorage layer 15 at the source side, not the drain side, of thenon-volatile memory cell.

Carrier injection efficiency and/or program efficiency is controlled bythe Schottky barrier at interfaces of silicide/silicon, Modifying theSchottky barrier at the source side may improve program efficiency. Themethods described herein may be combined with other techniques,including extra well dosage implantation, junction implantation, pocketimplantation and gate implantation. Methods will now be described formodifying characteristics of the Schottky barrier,

One method of modifying the Schottky barrier, as exemplified in FIGS.5A-5C, comprises controlling an overlap between the source/drain and thegate of a non-volatile memory cell. FIG. 5A is a cross-sectional diagramof a non-volatile memory cell of a type already introduced comprising asource 35, a drain 40, and a gate 21 with the source 35, the drain 40and a gate contact 45 formed of silicide. The cell is fabricated with agap 55 between a vertical extension of the drain 40 and an edge of thegate 21 nearest the drain 40. A similar gap may exist between a verticalextension of the source 35 and an edge of the gate 21 nearest the gate35. In the illustrated example, carriers must tunnel through arelatively large barrier in order to reach the storage layer 15, wherebybest programming efficiency in the illustrated embodiment may be foundby modifying the tunneling barrier. Tunneling behavior depends uponcharacteristics of materials and is relatively insensitive to devicescaling. In FIG. 5B, a similar memory cell structure is illustrated, butwith the Schottky junction (i.e., a source/substrate interface and/or adrain/substrate interface) being substantially aligned with an edge ofthe gate 21. In this case, a characteristic of the Schottky barrier maybe controlled by characteristics of interfaces between suicide andsilicon. According to yet another example, FIG. 5C illustrates a memorycell structure fabricated with an overlap 56 between the Schottkyjunction and the gate 21. That is, a vertical extension of an edge ofthe drain 40 overlaps an edge of the gate 21 nearest the drain 40.Again, a similar gap may exist between a vertical extension of an edgeof the source 35 and an edge of the gate 21 nearest the source 35.Working from this configuration, modifying bias conditions may improveprogramming efficiency.

Additional methods of modifying a Schottky barrier are diagrammed inFIGS. 6A-6C and described with reference to FIG. 7A a-7Cd. The flowdiagram of FIG. 6A presents an implementation of one method offabricating a memory cell employing a Schottky barrier. According to theillustrated implementation, which begins at step 100, conventionalstorage layer and gate processes may be performed at step 105 in amanner well understood by those skilled in the art. An active region maybe patterned at step 110 and a spacer may be formatted at step 115 usingknown methods. An example of a result of following steps 100, 105 and110 is illustrated in FIG. 1A. An implantation may be performed at step120 whereby atoms of a doping material are implanted in the structureresulting from (e.g., following) completion of step 115. FIG. 7A aillustrates one implementation of step 120 wherein an implant dosage 28is directed at the structure following step 115. Dopants implanted atstep 120 may be activated by employing, for example, a relativelylow-temperature thermal process. A silicide material 30 may be deposited(e.g., capped) on the structure of FIG. 7A b at step 130, followed byperformance of a thermal process at step 135 to format the silicidematerial 30 and create a silicide that defines a source 35, a drain 40,and agate contact 45. A Schottky barrier 43 modified by the doping mayform as a result, characteristics of which may be controlled bycontrolling (e.g., adjusting characteristics of) the steps of theimplementation of FIG. 6A. The implementation then or later (e.g.,ultimately) can be terminated at step 140.

An implementation of another method of fabricating a memory cell havinga modified Schottky barrier is described in the flow diagram of FIG. 68.Steps 200-220 of the implementation of FIG. 6B may be identical tocorresponding steps 100-120 of FIG. 6A, However, the implementation ofFIG, 6B deposits silicide material 30 (FIG. 7B b) at step 225 without astep of activating &pants implanted at step 220. The process can bediscerned from the schematics of FIGS. 7B a and 7Bb. A thermal processperformed at step 230 then may both format a silicide and activate the&wants, thereby creating a Schottky barrier 43 modified by the doping asshown in FIG. 7B c. The implementation of the method of FIG. 6B can beterminated at step 235,

A further implementation of yet another method of fabricating a memorycell that includes a modified Schottky barrier is depicted in the flowdiagram of FIG. 6C. Again, steps 300-315 in FIG. 6C may be identical tocorresponding steps 100-115 of FIG. 6A. At step 320, a suicide material30 is deposited over the structure formed after step 325 as illustratedin FIG. 7C a. The silicide material 30 may be formatted at step 325using a thermal process thereby forming a source, a drain and a gatecontact as shown in FIG. 7C b. An implantation step may then beperformed at step 330 as described in FIG. 7C c wherein an implantdosage 28 of doping material is applied to the structure of FIG. 7C b.The implantation may be activated at step 335 as shown in FIG. 7C d toform a Schottky barrier 43 modified by doping. The implementation of themethod can be terminated at step 340.

FIG. 8 illustrates yet another implementation of a method of fabricatinga memory cell with a modified Schottky barrier comprising agate process.The process described in the flow diagram of FIG. 8, which may beintegrated with any of the processes described above in connection withFIGS. 6A-6C, may act to adjust a gate workfunction. With reference toFIGS. 9A-9F, this implementation begins at step 400 and continues bydepositing gate material 20 (FIG. 9A) onto a charge trapping layer 15that overlies a substrate 10, which may be formed of for example,lightly doped or intrinsic silicon. The gate material 20 may comprisesilicon. A gate structure 23 may be patterned at step 410 using knownmethods as shown in FIG. 9B, and a spacer 25 may be formed on sides ofthe gate structure 23 at step 415, again using known methods to form thestructure depicted in FIG. 9C. Silicide material 30 may be deposited onthe result of step 415 as shown in FIG. 9D, and an implantation 28 ofdoping atoms may be introduced at step 425 (cf, FIG. 9E). An activationprocess, which may be a low-temperature thermal process, may beperformed at step 430 to activate the dopants and create a silicide thatforms a gate contact 45, a source 35, and a drain 40 as shown in FIG.9F. By extending a time duration of the activation process,substantially all of the gate material 20 may be silicided, resulting ina fully silicided (FUSI) gate 22. A Schottky barrier 43 modified bydoping may form between the source 35/drain 40 and the substrate 10. Asa variation on the method of FIG. 8, a metal gate may be formed toreplace the FUSI gate,

Summarizing the FIG. 6A, 6B, 6C and 8 Schottky-barrier modificationmethods, FIG. 6A describes an implantation and dosage activationfollowed by a silicidation process; FIG. 6B describes an implantation(and capping with silicide material) followed by simultaneousperformance of the dosage activation and silicidation; FIG. 6C describessilicidation followed by dosage implantation and activation processes;and FIG. 8 describes formation of a fully silicided gate to create amemory cell having a modified Schottky barrier. These techniques, whichmay operate to provide significant immunity to problems arising frommemory device miniaturization, support physical and electrical 1-hit and2-bit operation, and the resultant memory cells are easily implementedin or as NOR/NAND type flash memories. Further, these methods may applyto operation of any type of non-volatile memories including, forexample, floating gate and split gate structures.

In view of the foregoing, it will be understood by those skilled in theart that the methods of the present invention can facilitate formationand operation of non-volatile memory devices in an integrated circuit.In particular, the non-volatile memory devices may comprise dual bitcell structures. The above-described embodiments have been provided byway of example, and the present invention is not limited to theseexamples. Multiple variations and modification to the disclosedembodiments will occur, to the extent not mutually exclusive, to thoseskilled in the art upon consideration of the foregoing description.Additionally, other combinations, omissions, substitutions andmodifications will be apparent to the skilled artisan in view of thedisclosure herein. Accordingly, the present invention is not intended tobe limited by the disclosed embodiments, but is to be defined byreference to the appended claims.

1. A method of fabricating a non-volatile memory cell, the methodcomprising: providing a substrate; performing storage layer and gateprocesses over the substrate; implanting dopants into the substrate;capping with a silicide material over the substrate; and formatting thesilicide material; wherein a Schottky barrier is formed in thesubstrate.
 2. The method as set forth in claim 1, further comprisingactivating the dopants.
 3. The method as set forth in claim 1,comprising programming the non-volatile memory cell.
 4. The method asset forth in claim 3, wherein the programming comprises injecting hotcarriers.
 5. The method as set forth in claim 4, wherein the injectingcomprises one or more of injecting hot electrons and injecting hotholes.
 6. The method as set forth in claim 2, wherein the activatingoccurs during the formatting of the silicide material.
 7. The method asset forth in claim 2, wherein the implanting is performed after theformatting of the silicide material.
 8. The method as set forth in claim2, wherein the activating and the formatting comprise one or morelow-temperature processes.
 9. The method as set forth in claim 1,wherein the implanting is preceded by patterning an active region andformatting a spacer.
 10. The method as set forth in claim 1, wherein theimplanted dopants are activated by employing a relativelylow-temperature thermal process.
 11. The method as set forth in claim10, wherein the formatting comprises performing a thermal process toformat the silicide material.
 12. The method as set forth in claim 1,wherein the formatting occurs prior to activation of the implanteddopants.
 13. The method as set forth in claim 12, wherein the formattingcomprises performing a thermal process to activate the implanted dopantsand format the silicide material whereby the Schottky barrier ismodified by the dopant implantation and thermal process.
 14. The methodas set forth in claim 1, wherein the capping and formatting areperformed before the implanting.
 15. The method as set forth in claim14, wherein the capping is preceded by patterning an active region andformatting a spacer.
 16. The method as set forth in claim 15, whereinthe formatting of the silicide material comprises performing a thermalprocess.